1. Field of the Invention
The present invention relates to a cache memory unit, and more particularly to a cache memory unit for use in a multiprocessor.
2. Description of the Related Art
Generally, in a system employing a multiprocessor configuration, where the data in a main memory is rewritten by another processor, the contents in the main memory may not be the same as those in a cache memory. In order to avoid this, if the address is monitored on writes to the main memory (hereinafter referred to as "monitoring") and the data indicated by the address is registered in the cache memory, the data thus registered is required to be disposed of by a process such as invalidation so as to maintain the identity or consistency in the contents of stored data between the main memory and the cache memory.
A conventional cache memory unit for use in a system adopting a multiprocessor configuration is shown in FIG. 1. The data read from the main memory is copied to and held in a data memory 105. One line in FIG. 1 is one entry which is generally constituted by several bytes. The address information of the data held in the data memory 105 is stored in a tag memory 104 and whether the contents in the data memory 105 are valid or invalid is indicated by a valid flag 106.
For monitoring the data, the lower bits in the address data on the address bus 101 are decoded by a decoder 102 and one entry in the cache memory is selected by a monitoring select signal 103 outputted from the decoder 102. The address stored in the tag memory 104 in the selected entry and the upper bits of the address data on the address bus 101 are compared by a comparator 107 and, if they are in agreement, a hit signal 108 of an active level is outputted from the comparator 107. At this time, if a monitoring strobe signal 112 supplied from a strobe signal input terminal 113 is active, a monitoring clear signal 110 of an active level is outputted from an AND gate 111, so that the valid flag 106 is cleared. Normally, the strobe signal input terminal 113 receives a write signal from another processor and is informed that the data-rewriting has been made in the main memory.
An example of the arrangement in a conventional multiprocessor system is shown in FIG. 2. A first central processing unit (CPU) 202, a second CPU 204, a third CPU 205 and a main memory 203 are connected to a common address bus 101 and a common data bus 201. The conventional cache memory unit built in the microprocessor CPU 202 receives as the monitoring strobe signal 112 a write signal from other CPUs 204 and 205. If other CPUs rewrite in the main memory 203 and, by monitoring, if the rewritten data is recognized as having been registered in the cache memory, the valid flag of the entry in which such data is stored is cleared and the contents of such entry are invalidated, so that the consistency between the main memory and the cache memory is maintained.
Where a system is organized by using a microprocessor having a cache memory for a multiprocessor and an in-circuit emulator (hereinafter referred to as an "ICE") is used for debugging such a system, there are possibilities wherein the contents in the cache memory are invalidated by monitoring when the data entry is made also to an ICE dedicated memory by the interruption of the ICE. Naturally, the rate of cache hits in the course of execution of the user's program is lowered, so that the execution speed of the system becomes slower.
Now, it is assumed that the volume of the cache memory is 1 K-bytes (KB), the width of the data bus is 32 bits, one bus cycle for cache replacing is 2 clocks and the CPI (clocks per instruction) is 1. If the ICE interruption occurs after the cache memory of 1 KB has become full by the user's program and the writing is made to the ICE dedicated memory in such a way that all of the cache memory of 1 KB is invalidated, it takes at least 512 clocks for the cache memory of 1 KB to become full after the operation returns to the user's program. This means that there is about 50% reduction in the performance of the user's program.
There is also a problem in that, due to the occurrence of a lag in timing with respect to other normal system operations, it may become impossible to perform accurate debugging of the system.
Also, in order to control a monitoring strobe signal by recognizing the data entry into the ICE dedicated memory, it is necessary to provide a control circuit dedicated to the ICE in the system itself.